A flash memory cell has advantages similar to an erasable programmable read only memory (EPROM) and an electrically erasable and programmable read only memory (EEPROM). A flash memory cell includes a floating gate, an insulating layer, a control gate, a tunnel oxide layer, and an isolation layer formed over a silicon substrate. The flash memory cell also includes a source and drain region formed on an exposed portion of a silicon substrate. The flash memory cell can electrically store and erase 1-bit using one transistor.
The flash memory cell stores charges in the floating gate and the floating gate is insulated from the control gate. Data is stored and erased by applying power to the control gate which is coupled to the floating gate through the insulating material. The ratio of power transferred from the control gate to the floating gate through the insulating material is referred to as a coupling ratio. The value of the coupling ratio is proportional to the capacitance generated by an overlap between the floating gate and the control gate.
FIGS. 1A to 1D are flow diagrams showing a process of manufacturing a flash memory cell.
Referring to FIG. 1A, after a trench is formed by etching a predetermined region of a semiconductor substrate 100, a device isolation layer 102 is formed by a series of processes for burying an insulator into the trench. A first oxide layer 104, a first polycrystalline silicon layer 106, an insulating layer 108 and a photoresist pattern 110 for defining a floating gate are sequentially formed over the substrate 100 on which the device isolation layer 102 is formed. The first oxide layer 104 is deposited with a thickness ranging from approximately 90 Å to 100 Å and the first polycrystalline silicon layer 106 is deposited with a thickness ranging from approximately 950 Å to 1050 Å. The insulating layer 108 is deposited by using e.g., a nitride layer, a tetra ethyl ortho silicate (TEOS) or the like, at a thickness ranging from 2200 Å to 2300 Å.
After the insulating layer 108 is anisotropically etched along the photoresist pattern 110, the photoresist pattern 110 is removed by an ashing process using, e.g., Ar, O2 or the like, so that a floating gate region is defined through the patterned insulating layer 108, as shown in FIG. 1B.
After an insulator, e.g., TEOS or a nitride layer, is deposited on the semiconductor substrate 100 where a floating gate region is defined with a thickness ranging from approximately 740 Å to 760 Å, a spacer insulating layer 112 is formed on side surfaces of a patterned slot of the insulating layer 108 by performing reactive ion etching (RIE) on the deposited insulator, as shown in FIG. 1C.
Thereafter, as shown in FIG. 1D, a floating gate 106a is formed by etching the first polycrystalline silicon layer 106 and the first oxide layer 104 by using the insulating layer 108 and the spacer insulating layer 112 as a mask so that the device isolation layer 102 is exposed. Thereafter, a control gate 116 is formed by removing the spacer insulating layer 112 and the insulating layer 108 and by sequentially depositing a second insulating layer 114 and a second polycrystalline silicon layer on an upper surface of the semiconductor substrate 100.
Accordingly, for increasing a capacitance of a floating gate and a control gate, after an insulator is patterned through a photolithography process, a patterning process is repeatedly performed using an insulator to form a fine pattern. Accordingly, it takes long time to perform the manufacturing process and production yield is decreased due to a difficulty of forming the fine pattern.